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| author | Sanjay Patel <spatel@rotateright.com> | 2016-06-12 15:03:25 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-06-12 15:03:25 +0000 |
| commit | 977530a8c9e3e201f8094df9ab2306b1e699d821 (patch) | |
| tree | 6bf2df86885dd39b2e41e547ea148d14270bf617 /llvm/lib/CodeGen/MachineBlockPlacement.cpp | |
| parent | 1067986c5b2f6d25552a4f682331f70281024d28 (diff) | |
| download | bcm5719-llvm-977530a8c9e3e201f8094df9ab2306b1e699d821.tar.gz bcm5719-llvm-977530a8c9e3e201f8094df9ab2306b1e699d821.zip | |
[x86, SSE] change patterns for CMPP to float types to allow matching with SSE1 (PR28044)
This patch is intended to solve:
https://llvm.org/bugs/show_bug.cgi?id=28044
By changing the definition of X86ISD::CMPP to use float types, we allow it to be created
and pass legalization for an SSE1-only target where v4i32 is not legal.
The motivational trail for this change includes:
https://llvm.org/bugs/show_bug.cgi?id=28001
and eventually makes this trigger:
http://reviews.llvm.org/D21190
Ie, after this step, we should be free to have Clang generate FP compare IR instead of x86
intrinsics for SSE C packed compare intrinsics. (We can auto-upgrade and remove the LLVM
sse.cmp intrinsics as a follow-up step.) Once we're generating vector IR instead of x86
intrinsics, a big pile of generic optimizations can trigger.
Differential Revision: http://reviews.llvm.org/D21235
llvm-svn: 272511
Diffstat (limited to 'llvm/lib/CodeGen/MachineBlockPlacement.cpp')
0 files changed, 0 insertions, 0 deletions
