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| author | Sanjay Patel <spatel@rotateright.com> | 2015-09-25 21:49:48 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2015-09-25 21:49:48 +0000 |
| commit | bbbf9a1a34af09b6e271f2288c32429e1a53f3e6 (patch) | |
| tree | 18489b94ed026e4c10217aa4663e46fb1db27200 /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | d0626804fc04f89c0047db54ffd8a843da1f5b4a (diff) | |
| download | bcm5719-llvm-bbbf9a1a34af09b6e271f2288c32429e1a53f3e6.tar.gz bcm5719-llvm-bbbf9a1a34af09b6e271f2288c32429e1a53f3e6.zip | |
merge vector stores into wider vector stores and fix AArch64 misaligned access TLI hook (PR21711)
This is a redo of D7208 ( r227242 - http://llvm.org/viewvc/llvm-project?view=revision&revision=227242 ).
The patch was reverted because an AArch64 target could infinite loop after the change in DAGCombiner
to merge vector stores. That happened because AArch64's allowsMisalignedMemoryAccesses() wasn't telling
the truth. It reported all unaligned memory accesses as fast, but then split some 128-bit unaligned
accesses up in performSTORECombine() because they are slow.
This patch attempts to fix the problem in AArch's allowsMisalignedMemoryAccesses() while preserving
existing (perhaps questionable) lowering behavior.
The x86 test shows that store merging is working as intended for a target with fast 32-byte unaligned
stores.
Differential Revision: http://reviews.llvm.org/D12635
llvm-svn: 248622
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions
