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| author | Luke Cheeseman <luke.cheeseman@arm.com> | 2018-09-24 15:13:48 +0000 |
|---|---|---|
| committer | Luke Cheeseman <luke.cheeseman@arm.com> | 2018-09-24 15:13:48 +0000 |
| commit | ab7f9b170d854b8d5be55a94f48ad67727b4d0bc (patch) | |
| tree | 6d44732b826e08bc4aab1053980140e3dc4e458a /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | 1d0843c17575ebbd4c42abafb75097dd6dfba68d (diff) | |
| download | bcm5719-llvm-ab7f9b170d854b8d5be55a94f48ad67727b4d0bc.tar.gz bcm5719-llvm-ab7f9b170d854b8d5be55a94f48ad67727b4d0bc.zip | |
[Arm][AsmParser] Restrict register list size for VSTM/VLDM
- The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
- The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers
- This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52082
llvm-svn: 342891
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions
