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| author | Scott Michel <scottm@aero.org> | 2008-12-27 04:51:36 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2008-12-27 04:51:36 +0000 |
| commit | 8233527b0543795cbccb616c5ce647c26d6bbdca (patch) | |
| tree | a0c229bc13d85fe8677e2fececc0fba4f0075852 /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | f562b39e80314cda21cde145eda2d0f0a3f6fd19 (diff) | |
| download | bcm5719-llvm-8233527b0543795cbccb616c5ce647c26d6bbdca.tar.gz bcm5719-llvm-8233527b0543795cbccb616c5ce647c26d6bbdca.zip | |
- Remove Tilmann's custom truncate lowering: it completely hosed over
DAGcombine's ability to find reasons to remove truncates when they were not
needed. Consequently, the CellSPU backend would produce correct, but _really
slow and horrible_, code.
Replaced with instruction sequences that do the equivalent truncation in
SPUInstrInfo.td.
- Re-examine how unaligned loads and stores work. Generated unaligned
load code has been tested on the CellSPU hardware; see the i32operations.c
and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be
toy test code, it does prove that some real world code does compile
correctly.)
- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
fault because i64 ult is not yet implemented.)
- Added i64 eq and neq for setcc and select/setcc; started new instruction
information file for them in SPU64InstrInfo.td. Additional i64 operations
should be added to this file and not to SPUInstrInfo.td.
llvm-svn: 61447
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions
