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authorAlex Lorenz <arphaman@gmail.com>2015-08-19 18:55:47 +0000
committerAlex Lorenz <arphaman@gmail.com>2015-08-19 18:55:47 +0000
commite66a7ccf776b8d22819c4baa518a1d5825811c96 (patch)
tree99a6cfd9633af83e1982cd7e97439992edf381d4 /llvm/lib/CodeGen/MIRPrinter.cpp
parent27fd06922b161a5559fb3ac6ef8e5b85efc9da04 (diff)
downloadbcm5719-llvm-e66a7ccf776b8d22819c4baa518a1d5825811c96.tar.gz
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MIR Serialization: Serialize defined registers that require 'def' register flag.
The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
Diffstat (limited to 'llvm/lib/CodeGen/MIRPrinter.cpp')
-rw-r--r--llvm/lib/CodeGen/MIRPrinter.cpp11
1 files changed, 8 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index faeb9055c23..5d3c2999a11 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -116,7 +116,8 @@ public:
void printStackObjectReference(int FrameIndex);
void printOffset(int64_t Offset);
void printTargetFlags(const MachineOperand &Op);
- void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
+ void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
+ bool IsDef = false);
void print(const MachineMemOperand &Op);
void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
@@ -516,7 +517,7 @@ void MIPrinter::print(const MachineInstr &MI) {
++I) {
if (I)
OS << ", ";
- print(MI.getOperand(I), TRI);
+ print(MI.getOperand(I), TRI, /*IsDef=*/true);
}
if (I)
@@ -688,13 +689,17 @@ static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
return nullptr;
}
-void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
+void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
+ bool IsDef) {
printTargetFlags(Op);
switch (Op.getType()) {
case MachineOperand::MO_Register:
// FIXME: Serialize the tied register.
if (Op.isImplicit())
OS << (Op.isDef() ? "implicit-def " : "implicit ");
+ else if (!IsDef && Op.isDef())
+ // Print the 'def' flag only when the operand is defined after '='.
+ OS << "def ";
if (Op.isInternalRead())
OS << "internal ";
if (Op.isDead())
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