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authorCraig Topper <craig.topper@gmail.com>2015-12-05 07:13:35 +0000
committerCraig Topper <craig.topper@gmail.com>2015-12-05 07:13:35 +0000
commite5e035a3a86a8491b4e05395b73ec257438dc4af (patch)
treef2e2be1ac726e2830bcde551a8ff0bd160e108b5 /llvm/lib/CodeGen/MIRParser
parent58ee28410a29d9cd084c03d2dfb22aba53ef4029 (diff)
downloadbcm5719-llvm-e5e035a3a86a8491b4e05395b73ec257438dc4af.tar.gz
bcm5719-llvm-e5e035a3a86a8491b4e05395b73ec257438dc4af.zip
Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
llvm-svn: 254843
Diffstat (limited to 'llvm/lib/CodeGen/MIRParser')
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIParser.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index c9c2d62cec3..f2f6584fb6c 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -745,11 +745,11 @@ bool MIParser::verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands,
// Gather all the expected implicit operands.
SmallVector<MachineOperand, 4> ImplicitOperands;
if (MCID.ImplicitDefs)
- for (const uint16_t *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
+ for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
ImplicitOperands.push_back(
MachineOperand::CreateReg(*ImpDefs, true, true));
if (MCID.ImplicitUses)
- for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
+ for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
ImplicitOperands.push_back(
MachineOperand::CreateReg(*ImpUses, false, true));
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