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authorAlex Lorenz <arphaman@gmail.com>2015-08-11 00:32:49 +0000
committerAlex Lorenz <arphaman@gmail.com>2015-08-11 00:32:49 +0000
commitc48380878548ac69782f53823c4658f160f627d3 (patch)
tree92d8d89702a333ad2bfb8681ef4d2edb295985d9 /llvm/lib/CodeGen/MIRParser/MIRParser.cpp
parentd61c1f82801e1629e0187391c5aeb4c93311e024 (diff)
downloadbcm5719-llvm-c48380878548ac69782f53823c4658f160f627d3.tar.gz
bcm5719-llvm-c48380878548ac69782f53823c4658f160f627d3.zip
MIR Serialization: Serialize UsedPhysRegMask from the machine register info.
This commit serializes the UsedPhysRegMask register mask from the machine register information class. The mask is serialized as an inverted 'calleeSavedRegisters' mask to keep the output minimal. This commit also allows the MIR parser to infer this mask from the register mask operands if the machine function doesn't specify it. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244548
Diffstat (limited to 'llvm/lib/CodeGen/MIRParser/MIRParser.cpp')
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIRParser.cpp32
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index b5c7d2afefa..9b112e34b03 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -107,6 +107,9 @@ public:
const yaml::MachineFunction &YamlMF,
PerFunctionMIParsingState &PFS);
+ void inferRegisterInfo(MachineFunction &MF,
+ const yaml::MachineFunction &YamlMF);
+
bool initializeFrameInfo(MachineFunction &MF,
const yaml::MachineFunction &YamlMF,
PerFunctionMIParsingState &PFS);
@@ -339,6 +342,7 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
PFS))
return true;
}
+ inferRegisterInfo(MF, YamlMF);
// FIXME: This is a temporary workaround until the reserved registers can be
// serialized.
MF.getRegInfo().freezeReservedRegs(MF);
@@ -443,9 +447,37 @@ bool MIRParserImpl::initializeRegisterInfo(MachineFunction &MF,
}
RegInfo.addLiveIn(Reg, VReg);
}
+
+ // Parse the callee saved register mask.
+ BitVector CalleeSavedRegisterMask(RegInfo.getUsedPhysRegsMask().size());
+ if (!YamlMF.CalleeSavedRegisters)
+ return false;
+ for (const auto &RegSource : YamlMF.CalleeSavedRegisters.getValue()) {
+ unsigned Reg = 0;
+ if (parseNamedRegisterReference(Reg, SM, MF, RegSource.Value, PFS, IRSlots,
+ Error))
+ return error(Error, RegSource.SourceRange);
+ CalleeSavedRegisterMask[Reg] = true;
+ }
+ RegInfo.setUsedPhysRegMask(CalleeSavedRegisterMask.flip());
return false;
}
+void MIRParserImpl::inferRegisterInfo(MachineFunction &MF,
+ const yaml::MachineFunction &YamlMF) {
+ if (YamlMF.CalleeSavedRegisters)
+ return;
+ for (const MachineBasicBlock &MBB : MF) {
+ for (const MachineInstr &MI : MBB) {
+ for (const MachineOperand &MO : MI.operands()) {
+ if (!MO.isRegMask())
+ continue;
+ MF.getRegInfo().addPhysRegsUsedFromRegMask(MO.getRegMask());
+ }
+ }
+ }
+}
+
bool MIRParserImpl::initializeFrameInfo(MachineFunction &MF,
const yaml::MachineFunction &YamlMF,
PerFunctionMIParsingState &PFS) {
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