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author | Evan Cheng <evan.cheng@apple.com> | 2010-04-26 07:38:55 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-04-26 07:38:55 +0000 |
commit | ed69b382ea0a63398030649a4fa61b7756e39f70 (patch) | |
tree | cc551a6904b0251dad3914c88dcc289d4e1b5f3e /llvm/lib/CodeGen/LiveIntervalAnalysis.cpp | |
parent | 582565e991c76daa7fbb9d2364dcba0840ce1932 (diff) | |
download | bcm5719-llvm-ed69b382ea0a63398030649a4fa61b7756e39f70.tar.gz bcm5719-llvm-ed69b382ea0a63398030649a4fa61b7756e39f70.zip |
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
llvm-svn: 102323
Diffstat (limited to 'llvm/lib/CodeGen/LiveIntervalAnalysis.cpp')
-rw-r--r-- | llvm/lib/CodeGen/LiveIntervalAnalysis.cpp | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp index 1f00ccbbb01..9e6c70db403 100644 --- a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -1296,9 +1296,23 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, MachineOperand &O = ri.getOperand(); ++ri; if (MI->isDebugValue()) { - // Remove debug info for now. - O.setReg(0U); - DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI); + // Modify DBG_VALUE now that the value is in a spill slot. + uint64_t Offset = MI->getOperand(1).getImm(); + const MDNode *MDPtr = MI->getOperand(2).getMetadata(); + DebugLoc DL = MI->getDebugLoc(); + MachineInstr *NewDV = tii_->emitFrameIndexDebugValue(*mf_, Slot, Offset, + MDPtr, DL); + if (NewDV) { + DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI); + ReplaceMachineInstrInMaps(MI, NewDV); + MachineBasicBlock *MBB = MI->getParent(); + MBB->insert(MBB->erase(MI), NewDV); + } else { + DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI); + RemoveMachineInstrFromMaps(MI); + vrm.RemoveMachineInstrFromMaps(MI); + MI->eraseFromParent(); + } continue; } assert(!O.isImplicit() && "Spilling register that's used as implicit use?"); |