summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff options
context:
space:
mode:
authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-05-21 16:36:13 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-05-21 16:36:13 +0000
commita648c6a757e78fc5e3323cb0fd03885bfa01e91c (patch)
tree79f551e53c3462246b6759b5f2b710c8471aed88 /llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
parent1f3801062d61efde9fe10085fdec64acc640b602 (diff)
downloadbcm5719-llvm-a648c6a757e78fc5e3323cb0fd03885bfa01e91c.tar.gz
bcm5719-llvm-a648c6a757e78fc5e3323cb0fd03885bfa01e91c.zip
Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. llvm-svn: 104321
Diffstat (limited to 'llvm/lib/CodeGen/LiveIntervalAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions
OpenPOWER on IntegriCloud