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| author | Scott Michel <scottm@aero.org> | 2009-01-26 03:31:40 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2009-01-26 03:31:40 +0000 |
| commit | 9e3e4a9219dcb07ecbf0897cbd9d9b39d1cd9630 (patch) | |
| tree | 91caf5e19d12ca8baf4005987f658240ea13adbc /llvm/lib/CodeGen/LiveInterval.cpp | |
| parent | 624801e87e06c9f4436a2c3ad41289d5d3a82505 (diff) | |
| download | bcm5719-llvm-9e3e4a9219dcb07ecbf0897cbd9d9b39d1cd9630.tar.gz bcm5719-llvm-9e3e4a9219dcb07ecbf0897cbd9d9b39d1cd9630.zip | |
CellSPU:
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
selection (SPUISelDAGtoDAG.cpp).
<rant>DAGCombiner will insert all kinds of 64-bit optimizations after
operation legalization occurs and now we have to do most of the work that
instruction selection should be doing twice (once to determine if v2i64
build_vector can be handled by SelectCode(), which then runs all of the
predicates a second time to select the necessary instructions.) But,
CellSPU is a good citizen.</rant>
llvm-svn: 62990
Diffstat (limited to 'llvm/lib/CodeGen/LiveInterval.cpp')
0 files changed, 0 insertions, 0 deletions
