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author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-12-15 14:36:06 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-12-15 14:36:06 +0000 |
commit | 91b5cf8412a9fffdca96619f02f485c8c48bf852 (patch) | |
tree | 45cc792752ed1bae1559f8501bc5e485eda07fed /llvm/lib/CodeGen/LiveInterval.cpp | |
parent | 2f7f0e7a480d760999f1973d8db76aee590cf83e (diff) | |
download | bcm5719-llvm-91b5cf8412a9fffdca96619f02f485c8c48bf852.tar.gz bcm5719-llvm-91b5cf8412a9fffdca96619f02f485c8c48bf852.zip |
Extract LaneBitmask into a separate type
Specifically avoid implicit conversions from/to integral types to
avoid potential errors when changing the underlying type. For example,
a typical initialization of a "full" mask was "LaneMask = ~0u", which
would result in a value of 0x00000000FFFFFFFF if the type was extended
to uint64_t.
Differential Revision: https://reviews.llvm.org/D27454
llvm-svn: 289820
Diffstat (limited to 'llvm/lib/CodeGen/LiveInterval.cpp')
-rw-r--r-- | llvm/lib/CodeGen/LiveInterval.cpp | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/LiveInterval.cpp b/llvm/lib/CodeGen/LiveInterval.cpp index 509bf247948..8471260eac9 100644 --- a/llvm/lib/CodeGen/LiveInterval.cpp +++ b/llvm/lib/CodeGen/LiveInterval.cpp @@ -876,7 +876,7 @@ void LiveInterval::computeSubRangeUndefs(SmallVectorImpl<SlotIndex> &Undefs, const SlotIndexes &Indexes) const { assert(TargetRegisterInfo::isVirtualRegister(reg)); LaneBitmask VRegMask = MRI.getMaxLaneMaskForVReg(reg); - assert((VRegMask & LaneMask) != 0); + assert(!(VRegMask & LaneMask).none()); const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); for (const MachineOperand &MO : MRI.def_operands(reg)) { if (!MO.isUndef()) @@ -885,7 +885,7 @@ void LiveInterval::computeSubRangeUndefs(SmallVectorImpl<SlotIndex> &Undefs, assert(SubReg != 0 && "Undef should only be set on subreg defs"); LaneBitmask DefMask = TRI.getSubRegIndexLaneMask(SubReg); LaneBitmask UndefMask = VRegMask & ~DefMask; - if ((UndefMask & LaneMask) != 0) { + if (!(UndefMask & LaneMask).none()) { const MachineInstr &MI = *MO.getParent(); bool EarlyClobber = MO.isEarlyClobber(); SlotIndex Pos = Indexes.getInstructionIndex(MI).getRegSlot(EarlyClobber); @@ -982,15 +982,16 @@ void LiveInterval::verify(const MachineRegisterInfo *MRI) const { super::verify(); // Make sure SubRanges are fine and LaneMasks are disjunct. - LaneBitmask Mask = 0; - LaneBitmask MaxMask = MRI != nullptr ? MRI->getMaxLaneMaskForVReg(reg) : ~0u; + LaneBitmask Mask; + LaneBitmask MaxMask = MRI != nullptr ? MRI->getMaxLaneMaskForVReg(reg) + : LaneBitmask::getAll(); for (const SubRange &SR : subranges()) { // Subrange lanemask should be disjunct to any previous subrange masks. - assert((Mask & SR.LaneMask) == 0); + assert((Mask & SR.LaneMask).none()); Mask |= SR.LaneMask; // subrange mask should not contained in maximum lane mask for the vreg. - assert((Mask & ~MaxMask) == 0); + assert((Mask & ~MaxMask).none()); // empty subranges must be removed. assert(!SR.empty()); |