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author | Lei Huang <lei@ca.ibm.com> | 2018-10-26 18:09:36 +0000 |
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committer | Lei Huang <lei@ca.ibm.com> | 2018-10-26 18:09:36 +0000 |
commit | de20843f6fe53795e27f4ddfc2a550b3497aee02 (patch) | |
tree | 28d7ce9844ff737cb9e88596c2c513ebf67a8cde /llvm/lib/CodeGen/LexicalScopes.cpp | |
parent | 3cc0e935c4d82836a8476a7aac3d51845755d8d0 (diff) | |
download | bcm5719-llvm-de20843f6fe53795e27f4ddfc2a550b3497aee02.tar.gz bcm5719-llvm-de20843f6fe53795e27f4ddfc2a550b3497aee02.zip |
[PowerPC] Improve BUILD_VECTOR of 4 i32s
Currently, for this node:
vector int test(int a, int b, int c, int d) {
return (vector int) { a, b, c, d };
}
we get this on Power9:
mtvsrdd 34, 5, 3
mtvsrdd 35, 6, 4
vmrgow 2, 3, 2
and this on Power8:
mtvsrwz 0, 3
mtvsrwz 1, 5
mtvsrwz 2, 4
mtvsrwz 3, 6
xxmrghd 34, 1, 0
xxmrghd 35, 3, 2
vmrgow 2, 3, 2
This can be improved to this on LE Power9:
rldimi 3, 4, 32, 0
rldimi 5, 6, 32, 0
mtvsrdd 34, 5, 3
and this on LE Power8
rldimi 3, 4, 32, 0
rldimi 5, 6, 32, 0
mtvsrd 34, 3
mtvsrd 35, 5
xxpermdi 34, 35, 34, 0
This patch updates the TD pattern to generate the optimized sequence for both
Power8 and Power9 on LE and BE.
Differential Revision: https://reviews.llvm.org/D53494
llvm-svn: 345414
Diffstat (limited to 'llvm/lib/CodeGen/LexicalScopes.cpp')
0 files changed, 0 insertions, 0 deletions