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authorEvan Cheng <evan.cheng@apple.com>2009-09-30 08:49:50 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-09-30 08:49:50 +0000
commitf305ead1cce10fd3f82dbf46cd956d4551711b0d (patch)
tree0c82152c520ec59c46cae3900c9b61a21309a5f3 /llvm/lib/CodeGen/LLVMTargetMachine.cpp
parent3ea1ba7739bc2fbaebbc4b3ceff4925437f0c8f1 (diff)
downloadbcm5719-llvm-f305ead1cce10fd3f82dbf46cd956d4551711b0d.tar.gz
bcm5719-llvm-f305ead1cce10fd3f82dbf46cd956d4551711b0d.zip
Add a target hook to add pre- post-regalloc scheduling passes.
llvm-svn: 83144
Diffstat (limited to 'llvm/lib/CodeGen/LLVMTargetMachine.cpp')
-rw-r--r--llvm/lib/CodeGen/LLVMTargetMachine.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
index a38d8ccab78..4e713a6ed31 100644
--- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
@@ -317,6 +317,10 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createPrologEpilogCodeInserter());
printAndVerify(PM);
+ // Run pre-sched2 passes.
+ if (addPreSched2(PM, OptLevel))
+ printAndVerify(PM);
+
// Second pass scheduler.
if (OptLevel != CodeGenOpt::None) {
PM.add(createPostRAScheduler());
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