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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-02-10 18:58:34 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-02-10 18:58:34 +0000
commita16ae59722df8a1adf0d0830a4490ea16381bae1 (patch)
tree065c05312ccc824c3b4542e4e7d37f13c6fba55f /llvm/lib/CodeGen/InterferenceCache.h
parentb7c1715df11a98915d12d7f5f775045444e78b09 (diff)
downloadbcm5719-llvm-a16ae59722df8a1adf0d0830a4490ea16381bae1.tar.gz
bcm5719-llvm-a16ae59722df8a1adf0d0830a4490ea16381bae1.zip
Add register mask support to InterferenceCache.
This makes global live range splitting behave identically with and without register mask operands. This is not necessarily the best way of using register masks for live range splitting. It would be more efficient to first split global live ranges around calls (i.e., register masks), and reserve the fine grained per-physreg interference guidance for global live ranges that do not cross calls. For now the goal is to produce identical assembly when enabling register masks. llvm-svn: 150259
Diffstat (limited to 'llvm/lib/CodeGen/InterferenceCache.h')
-rw-r--r--llvm/lib/CodeGen/InterferenceCache.h12
1 files changed, 9 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/InterferenceCache.h b/llvm/lib/CodeGen/InterferenceCache.h
index 437f9848b03..485a325aa14 100644
--- a/llvm/lib/CodeGen/InterferenceCache.h
+++ b/llvm/lib/CodeGen/InterferenceCache.h
@@ -18,6 +18,8 @@
namespace llvm {
+class LiveIntervals;
+
class InterferenceCache {
const TargetRegisterInfo *TRI;
LiveIntervalUnion *LIUArray;
@@ -51,6 +53,9 @@ class InterferenceCache {
/// Indexes - Mapping block numbers to SlotIndex ranges.
SlotIndexes *Indexes;
+ /// LIS - Used for accessing register mask interference maps.
+ LiveIntervals *LIS;
+
/// PrevPos - The previous position the iterators were moved to.
SlotIndex PrevPos;
@@ -70,13 +75,14 @@ class InterferenceCache {
void update(unsigned MBBNum);
public:
- Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0) {}
+ Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
- void clear(MachineFunction *mf, SlotIndexes *indexes) {
+ void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
assert(!hasRefs() && "Cannot clear cache entry with references");
PhysReg = 0;
MF = mf;
Indexes = indexes;
+ LIS = lis;
}
unsigned getPhysReg() const { return PhysReg; }
@@ -126,7 +132,7 @@ public:
InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {}
/// init - Prepare cache for a new function.
- void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*,
+ void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*, LiveIntervals*,
const TargetRegisterInfo *);
/// getMaxCursors - Return the maximum number of concurrent cursors that can
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