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author | Tim Northover <tnorthover@apple.com> | 2016-08-26 17:46:13 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2016-08-26 17:46:13 +0000 |
commit | cecee56abb688cd98f0dc9334acdfec8831f7ddd (patch) | |
tree | 17e1fa4c89a21a4b8041b088bd8d3d7a35e96bfd /llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp | |
parent | 7a753d9bec529698c16475c72cf1de386b63381f (diff) | |
download | bcm5719-llvm-cecee56abb688cd98f0dc9334acdfec8831f7ddd.tar.gz bcm5719-llvm-cecee56abb688cd98f0dc9334acdfec8831f7ddd.zip |
GlobalISel: legalize sdiv and srem operations.
llvm-svn: 279842
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp index 401f29a6ddc..ec59c834296 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp @@ -42,6 +42,8 @@ MachineLegalizeHelper::legalizeInstrStep(MachineInstr &MI, return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action)); case MachineLegalizer::WidenScalar: return widenScalar(MI, std::get<1>(Action), std::get<2>(Action)); + case MachineLegalizer::Lower: + return lower(MI, std::get<1>(Action), std::get<2>(Action)); case MachineLegalizer::FewerElements: return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action)); default: @@ -269,6 +271,33 @@ MachineLegalizeHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, } MachineLegalizeHelper::LegalizeResult +MachineLegalizeHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { + using namespace TargetOpcode; + unsigned Size = Ty.getSizeInBits(); + MIRBuilder.setInstr(MI); + + switch(MI.getOpcode()) { + default: + return UnableToLegalize; + case TargetOpcode::G_SREM: + case TargetOpcode::G_UREM: { + unsigned QuotReg = MRI.createGenericVirtualRegister(Size); + MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, Ty) + .addDef(QuotReg) + .addUse(MI.getOperand(1).getReg()) + .addUse(MI.getOperand(2).getReg()); + + unsigned ProdReg = MRI.createGenericVirtualRegister(Size); + MIRBuilder.buildMul(Ty, ProdReg, QuotReg, MI.getOperand(2).getReg()); + MIRBuilder.buildSub(Ty, MI.getOperand(0).getReg(), + MI.getOperand(1).getReg(), ProdReg); + MI.eraseFromParent(); + return Legalized; + } + } +} + +MachineLegalizeHelper::LegalizeResult MachineLegalizeHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { assert(TypeIdx == 0 && "don't know how to handle secondary types yet"); |