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author | Tim Northover <tnorthover@apple.com> | 2016-08-04 20:54:13 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2016-08-04 20:54:13 +0000 |
commit | 9656f1476cbcba7898f16062e3b6e5be92eecb78 (patch) | |
tree | 05feb60c9788170ae1d1d28f7b88026e68c6e6d2 /llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | |
parent | 404f1b7db566651464efbc6aa2a195bc444e3ba2 (diff) | |
download | bcm5719-llvm-9656f1476cbcba7898f16062e3b6e5be92eecb78.tar.gz bcm5719-llvm-9656f1476cbcba7898f16062e3b6e5be92eecb78.zip |
GlobalISel: implement narrowing for G_ADD.
llvm-svn: 277769
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 09a8fa6001b..5abc652303e 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -95,6 +95,11 @@ MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) { return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op); } +MachineInstrBuilder MachineIRBuilder::buildConstant(LLT Ty, unsigned Res, + int64_t Val) { + return buildInstr(TargetOpcode::G_CONSTANT, Ty).addDef(Res).addImm(Val); +} + MachineInstrBuilder MachineIRBuilder::buildBrCond(LLT Ty, unsigned Tst, MachineBasicBlock &Dest) { return buildInstr(TargetOpcode::G_BRCOND, Ty).addUse(Tst).addMBB(&Dest); @@ -119,6 +124,18 @@ MachineInstrBuilder MachineIRBuilder::buildStore(LLT VTy, LLT PTy, .addMemOperand(&MMO); } +MachineInstrBuilder MachineIRBuilder::buildAdde(LLT Ty, unsigned Res, + unsigned CarryOut, unsigned Op0, + unsigned Op1, + unsigned CarryIn) { + return buildInstr(TargetOpcode::G_ADDE, Ty) + .addDef(Res) + .addDef(CarryOut) + .addUse(Op0) + .addUse(Op1) + .addUse(CarryIn); +} + MachineInstrBuilder MachineIRBuilder::buildAnyExtend(LLT Ty, unsigned Res, unsigned Op) { return buildInstr(TargetOpcode::G_ANYEXTEND, Ty).addDef(Res).addUse(Op); |