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authorQuentin Colombet <qcolombet@apple.com>2016-02-11 21:16:56 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-02-11 21:16:56 +0000
commit8fd6718700449a39c1af00a32569950fa4d501c0 (patch)
treea48864daf0d6a49555bbd7c4b88ccf8652cb7eb1 /llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
parente3ddf4c25d33ddb6fee572c31824dd4b6c583d4e (diff)
downloadbcm5719-llvm-8fd6718700449a39c1af00a32569950fa4d501c0.tar.gz
bcm5719-llvm-8fd6718700449a39c1af00a32569950fa4d501c0.zip
[Target] Add a helper function to check if an opcode is invalid after isel.
llvm-svn: 260590
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp')
-rw-r--r--llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp14
1 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 293e8e74470..ded64077979 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -15,6 +15,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
@@ -62,14 +63,22 @@ MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty,
unsigned Op1) {
MachineInstr *NewMI =
BuildMI(getMF(), DL, getTII().get(Opcode), Res).addReg(Op0).addReg(Op1);
- if (Ty)
+ if (Ty) {
+ assert(isPreISelGenericOpcode(Opcode) &&
+ "Only generic instruction can have a type");
NewMI->setType(Ty);
+ } else
+ assert(!isPreISelGenericOpcode(Opcode) &&
+ "Generic instruction must have a type");
getMBB().insert(getInsertPt(), NewMI);
return NewMI;
}
MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res,
unsigned Op0) {
+ assert(!isPreISelGenericOpcode(Opcode) &&
+ "Generic instruction must have a type");
+
MachineInstr *NewMI =
BuildMI(getMF(), DL, getTII().get(Opcode), Res).addReg(Op0);
getMBB().insert(getInsertPt(), NewMI);
@@ -77,6 +86,9 @@ MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res,
}
MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode) {
+ assert(!isPreISelGenericOpcode(Opcode) &&
+ "Generic instruction must have a type");
+
MachineInstr *NewMI = BuildMI(getMF(), DL, getTII().get(Opcode));
getMBB().insert(getInsertPt(), NewMI);
return NewMI;
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