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author | Tim Northover <tnorthover@apple.com> | 2016-07-22 20:03:43 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2016-07-22 20:03:43 +0000 |
commit | 33b07d6725ab32e20ebeb62707be21c35a66390c (patch) | |
tree | 3347fbfe37618df37e8da560e0e29c65fda6d3c1 /llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | |
parent | e4a4f33daf7f05a058d7d72e5a3019f1194b597b (diff) | |
download | bcm5719-llvm-33b07d6725ab32e20ebeb62707be21c35a66390c.tar.gz bcm5719-llvm-33b07d6725ab32e20ebeb62707be21c35a66390c.zip |
GlobalISel: implement legalization pass, with just one transformation.
This adds the actual MachineLegalizeHelper to do the work and a trivial pass
wrapper that legalizes all instructions in a MachineFunction. Currently the
only transformation supported is splitting up a vector G_ADD into one acting on
smaller vectors.
llvm-svn: 276461
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 220965ce660..2b91584c75d 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -110,3 +110,35 @@ MachineInstr *MachineIRBuilder::buildFrameIndex(LLT Ty, unsigned Res, int Idx) { MIB.addImm(Idx); return NewMI; } + +MachineInstr *MachineIRBuilder::buildAdd(LLT Ty, unsigned Res, unsigned Op0, + unsigned Op1) { + return buildInstr(TargetOpcode::G_ADD, Ty, Res, Op0, Op1); +} + +MachineInstr *MachineIRBuilder::buildExtract(LLT Ty, ArrayRef<unsigned> Results, + unsigned Src, + ArrayRef<unsigned> Indexes) { + assert(Results.size() == Indexes.size() && "inconsistent number of regs"); + + MachineInstr *NewMI = buildInstr(TargetOpcode::G_EXTRACT, Ty); + auto MIB = MachineInstrBuilder(getMF(), NewMI); + for (auto Res : Results) + MIB.addReg(Res, RegState::Define); + + MIB.addReg(Src); + + for (auto Idx : Indexes) + MIB.addImm(Idx); + return NewMI; +} + +MachineInstr *MachineIRBuilder::buildSequence(LLT Ty, unsigned Res, + ArrayRef<unsigned> Ops) { + MachineInstr *NewMI = buildInstr(TargetOpcode::G_SEQUENCE, Ty); + auto MIB = MachineInstrBuilder(getMF(), NewMI); + MIB.addReg(Res, RegState::Define); + for (auto Op : Ops) + MIB.addReg(Op); + return NewMI; +} |