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| author | Jessica Paquette <jpaquette@apple.com> | 2019-07-26 23:28:53 +0000 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2019-07-26 23:28:53 +0000 |
| commit | aa8b9993c23f9915f1ba694502333f67a627e8d0 (patch) | |
| tree | 7a620a39ac88ac1fd39f18b1e1511313349ce7f7 /llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | |
| parent | f5a338369be46be25ed761617c00b7d9db45111e (diff) | |
| download | bcm5719-llvm-aa8b9993c23f9915f1ba694502333f67a627e8d0.tar.gz bcm5719-llvm-aa8b9993c23f9915f1ba694502333f67a627e8d0.zip | |
[AArch64][GlobalISel] Select @llvm.aarch64.stlxr for 32-bit pointers
Add partial instruction selection for intrinsics like this:
```
declare i32 @llvm.aarch64.stlxr(i64, i32*)
```
(This only handles the case where a G_ZEXT is feeding the intrinsic.)
Also make sure that the added store instruction actually has the memory op from
the original G_STORE.
Update select-stlxr-intrin.mir and arm64-ldxr-stxr.ll.
Differential Revision: https://reviews.llvm.org/D65355
llvm-svn: 367163
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp')
0 files changed, 0 insertions, 0 deletions
