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authorTim Northover <tnorthover@apple.com>2016-08-15 21:13:17 +0000
committerTim Northover <tnorthover@apple.com>2016-08-15 21:13:17 +0000
commit28fdc4272d598bdb7b0696ac22c20e9a41836c03 (patch)
tree2d53633f14414e74c2ba78479b045eaeed7f5c71 /llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
parentad71543972e1f6c8587ef13ce9547eafc79d7fab (diff)
downloadbcm5719-llvm-28fdc4272d598bdb7b0696ac22c20e9a41836c03.tar.gz
bcm5719-llvm-28fdc4272d598bdb7b0696ac22c20e9a41836c03.zip
GlobalISel: support loads and stores of strange types.
Before we mischaracterized structs and i1 types as a scalar with size 0 in various ways. llvm-svn: 278744
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp')
-rw-r--r--llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp19
1 files changed, 10 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 3f396cce36b..ee5e8d67c85 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -45,7 +45,6 @@ unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
// we need to concat together to produce the value.
assert(Val.getType()->isSized() &&
"Don't know how to create an empty vreg");
- assert(!Val.getType()->isAggregateType() && "Not yet implemented");
unsigned Size = DL->getTypeSizeInBits(Val.getType());
unsigned VReg = MRI->createGenericVirtualRegister(Size);
ValReg = VReg;
@@ -139,13 +138,13 @@ bool IRTranslator::translateLoad(const User &U) {
MachineFunction &MF = MIRBuilder.getMF();
unsigned Res = getOrCreateVReg(LI);
unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
- LLT VTy{*LI.getType()}, PTy{*LI.getPointerOperand()->getType()};
+ LLT VTy{*LI.getType(), DL}, PTy{*LI.getPointerOperand()->getType()};
MIRBuilder.buildLoad(
VTy, PTy, Res, Addr,
- *MF.getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
- MachineMemOperand::MOLoad,
- VTy.getSizeInBits() / 8, getMemOpAlignment(LI)));
+ *MF.getMachineMemOperand(
+ MachinePointerInfo(LI.getPointerOperand()), MachineMemOperand::MOLoad,
+ DL->getTypeStoreSize(LI.getType()), getMemOpAlignment(LI)));
return true;
}
@@ -156,14 +155,16 @@ bool IRTranslator::translateStore(const User &U) {
MachineFunction &MF = MIRBuilder.getMF();
unsigned Val = getOrCreateVReg(*SI.getValueOperand());
unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
- LLT VTy{*SI.getValueOperand()->getType()},
+ LLT VTy{*SI.getValueOperand()->getType(), DL},
PTy{*SI.getPointerOperand()->getType()};
MIRBuilder.buildStore(
VTy, PTy, Val, Addr,
- *MF.getMachineMemOperand(MachinePointerInfo(SI.getPointerOperand()),
- MachineMemOperand::MOStore,
- VTy.getSizeInBits() / 8, getMemOpAlignment(SI)));
+ *MF.getMachineMemOperand(
+ MachinePointerInfo(SI.getPointerOperand()),
+ MachineMemOperand::MOStore,
+ DL->getTypeStoreSize(SI.getValueOperand()->getType()),
+ getMemOpAlignment(SI)));
return true;
}
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