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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-05-24 09:17:23 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-05-24 09:17:23 +0000 |
| commit | 968cb0e0499436cdbe4dd97e61b1ffb8abd5817c (patch) | |
| tree | 36d1b64133dfb26288fa26e8e442c5379352be6c /llvm/lib/CodeGen/CodeGenPrepare.cpp | |
| parent | 6bca64fe5e9cf04cd39217e5ae2e148dc96b7dae (diff) | |
| download | bcm5719-llvm-968cb0e0499436cdbe4dd97e61b1ffb8abd5817c.tar.gz bcm5719-llvm-968cb0e0499436cdbe4dd97e61b1ffb8abd5817c.zip | |
[AArch64][SVE2] Asm: add various bitwise shift instructions
Summary:
This patch adds support for the SVE2 saturating/rounding bitwise shift
left (predicated) group of instructions:
* SRSHL, URSHL, SRSHLR, URSHLR, SQSHL, UQSHL, SQRSHL, UQRSHL,
SQSHLR, UQSHLR, SQRSHLR, UQRSHLR
Immediate forms of the SQSHL and UQSHL instructions are also added to
the existing SVE bitwise shift by immediate (predicated) group, as well
as three new instructions SRSHR/URSHR/SQSHLU. The new instructions in
this group are encoded similarly and are implemented using the same
TableGen class with a minimal change (1 bit in encoding).
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62140
llvm-svn: 361612
Diffstat (limited to 'llvm/lib/CodeGen/CodeGenPrepare.cpp')
0 files changed, 0 insertions, 0 deletions
