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| author | Hao Liu <Hao.Liu@arm.com> | 2015-06-26 02:10:27 +0000 |
|---|---|---|
| committer | Hao Liu <Hao.Liu@arm.com> | 2015-06-26 02:10:27 +0000 |
| commit | 1c1e0c9e71d09581b93b4e0d13fafd06cb28fe64 (patch) | |
| tree | 5ab1b8e9feec140d3669aebb585713a14025e18b /llvm/lib/CodeGen/CMakeLists.txt | |
| parent | aaa68a60a95bc02ed226a5050bb4eddcf51697c0 (diff) | |
| download | bcm5719-llvm-1c1e0c9e71d09581b93b4e0d13fafd06cb28fe64.tar.gz bcm5719-llvm-1c1e0c9e71d09581b93b4e0d13fafd06cb28fe64.zip | |
[InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics.
E.g. An interleaved load (Factor = 2):
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
%v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.
E.g. An interleaved store (Factor = 3):
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.
Differential Revision: http://reviews.llvm.org/D10533
llvm-svn: 240751
Diffstat (limited to 'llvm/lib/CodeGen/CMakeLists.txt')
| -rw-r--r-- | llvm/lib/CodeGen/CMakeLists.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt index a992c5e00b2..eb7552970d3 100644 --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -30,6 +30,7 @@ add_llvm_library(LLVMCodeGen ImplicitNullChecks.cpp InlineSpiller.cpp InterferenceCache.cpp + InterleavedAccessPass.cpp IntrinsicLowering.cpp LLVMTargetMachine.cpp LatencyPriorityQueue.cpp |
