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author | Sanjay Patel <spatel@rotateright.com> | 2019-09-10 13:00:31 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2019-09-10 13:00:31 +0000 |
commit | df6a958dcb56daf59cbaeb7870d80f7a73854cda (patch) | |
tree | a07127199aa0f53db066841a664800d5a33a63d0 /llvm/lib/CodeGen/BreakFalseDeps.cpp | |
parent | 5d269590395229743b3c21f1d74dc3912dc680fa (diff) | |
download | bcm5719-llvm-df6a958dcb56daf59cbaeb7870d80f7a73854cda.tar.gz bcm5719-llvm-df6a958dcb56daf59cbaeb7870d80f7a73854cda.zip |
[BreakFalseDeps] fix typos/grammar in documentation comment; NFC
llvm-svn: 371516
Diffstat (limited to 'llvm/lib/CodeGen/BreakFalseDeps.cpp')
-rw-r--r-- | llvm/lib/CodeGen/BreakFalseDeps.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp index a65b3447bab..382f76da321 100644 --- a/llvm/lib/CodeGen/BreakFalseDeps.cpp +++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp @@ -9,12 +9,11 @@ /// \file Break False Dependency pass. /// /// Some instructions have false dependencies which cause unnecessary stalls. -/// For exmaple, instructions that only write part of a register, and implicitly -/// need to read the other parts of the register. This may cause unwanted +/// For example, instructions may write part of a register and implicitly +/// need to read the other parts of the register. This may cause unwanted /// stalls preventing otherwise unrelated instructions from executing in /// parallel in an out-of-order CPU. -/// This pass is aimed at identifying and avoiding these depepndencies when -/// possible. +/// This pass is aimed at identifying and avoiding these dependencies. // //===----------------------------------------------------------------------===// |