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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-27 10:25:02 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-27 10:25:02 +0000 |
| commit | ccb71b2985a2a5073cedd1d734fb0fc2712d68f0 (patch) | |
| tree | ceece4e12f9af39814a7e1b5b2b0a380de5495c4 /llvm/lib/CodeGen/BranchFolding.cpp | |
| parent | ab0f18076b11972429e7d04cb818582f949f03b5 (diff) | |
| download | bcm5719-llvm-ccb71b2985a2a5073cedd1d734fb0fc2712d68f0.tar.gz bcm5719-llvm-ccb71b2985a2a5073cedd1d734fb0fc2712d68f0.zip | |
Revert rL356864 : [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)
Enable SSE41 ZERO_EXTEND_VECTOR_INREG shuffle combines - for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern we reduce the shuffles (port5-bottleneck on Intel) at the expense of creating a zero (pxor v,v) and an extra register move - which is a good trade off as these are pretty cheap and in most cases it doesn't increase register pressure.
This also exposed a missed opportunity to use combine to ZERO_EXTEND_VECTOR_INREG with folded loads - even if we're in the float domain.
........
Causes PR41249
llvm-svn: 357057
Diffstat (limited to 'llvm/lib/CodeGen/BranchFolding.cpp')
0 files changed, 0 insertions, 0 deletions
