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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-10-22 00:28:59 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-10-22 00:28:59 +0000
commit8226ca29e20060d4ddd8a3d8879a09553c2bc83e (patch)
treeea5f0f8665552f0d67104891983141e16dd5ee07 /llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
parent9886b0da3b760077633f0db63fcf33b1b3dcc118 (diff)
downloadbcm5719-llvm-8226ca29e20060d4ddd8a3d8879a09553c2bc83e.tar.gz
bcm5719-llvm-8226ca29e20060d4ddd8a3d8879a09553c2bc83e.zip
Fix typo
llvm-svn: 220353
Diffstat (limited to 'llvm/lib/CodeGen/BasicTargetTransformInfo.cpp')
-rw-r--r--llvm/lib/CodeGen/BasicTargetTransformInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/BasicTargetTransformInfo.cpp b/llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
index 190e38bd8c1..b9b1fd838d7 100644
--- a/llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
+++ b/llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
@@ -589,7 +589,7 @@ unsigned BasicTTI::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
// The operation is legal. Assume it costs 1.
- // If the type is split to multiple registers, assume that thre is some
+ // If the type is split to multiple registers, assume that there is some
// overhead to this.
// TODO: Once we have extract/insert subvector cost we need to use them.
if (LT.first > 1)
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