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| author | Sam Parker <sam.parker@arm.com> | 2018-04-09 08:16:11 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2018-04-09 08:16:11 +0000 |
| commit | 1f4f4d9a080cc9ea27c1040ec1c7341a29d77487 (patch) | |
| tree | 83628e026317a5bebc4b9c22aea961c82269c974 /llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | |
| parent | 324edae831410c7d7e37d446656f948b36d2e56c (diff) | |
| download | bcm5719-llvm-1f4f4d9a080cc9ea27c1040ec1c7341a29d77487.tar.gz bcm5719-llvm-1f4f4d9a080cc9ea27c1040ec1c7341a29d77487.zip | |
[DAGCombine] Improve ReduceLoad for SRL
Recommitting r329283, third time lucky...
If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.
Differential Revision: https://reviews.llvm.org/D41350
llvm-svn: 329551
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp')
0 files changed, 0 insertions, 0 deletions
