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authorJacques Pienaar <jpienaar@google.com>2016-11-29 23:01:09 +0000
committerJacques Pienaar <jpienaar@google.com>2016-11-29 23:01:09 +0000
commitfc13bdd2db3035fc3693fec6aa086db4d1db3e4c (patch)
tree79f5be8b63bf49f0aeaa4bf76936dd921e2091de /llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
parentf57f150b1b4c357ca50291d17f16dfb5dd735527 (diff)
downloadbcm5719-llvm-fc13bdd2db3035fc3693fec6aa086db4d1db3e4c.tar.gz
bcm5719-llvm-fc13bdd2db3035fc3693fec6aa086db4d1db3e4c.zip
[lanai] Manually match 0/-1 with R0/R1.
Summary: Previously 0 and -1 was matched via tablegen rules. But this could cause problems where a physical register was being used where a virtual register was expected (seen in optimizeSelect and TwoAddressInstructionPass). Instead follow AArch64 and match in DAGToDAGISel. Reviewers: eliben, majnemer Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27171 llvm-svn: 288215
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp')
0 files changed, 0 insertions, 0 deletions
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