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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-07-31 18:05:56 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-07-31 18:05:56 +0000 |
| commit | 5d9b00d15b3d449e8e2eadd5fa7d5d986970418f (patch) | |
| tree | dbf4ac4afe1a01f70752387d5fd8c20738ab559d /llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp | |
| parent | 7f97570e79fffc25e204617714be2355f4af4c47 (diff) | |
| download | bcm5719-llvm-5d9b00d15b3d449e8e2eadd5fa7d5d986970418f.tar.gz bcm5719-llvm-5d9b00d15b3d449e8e2eadd5fa7d5d986970418f.zip | |
[X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)
As was done for vector rotations, we can efficiently use ISD::MULHU for vXi8/vXi16 ISD::SRL lowering.
Shift-by-zero cases are still problematic (mainly on v32i8 due to extra AND/ANDN/OR or VPBLENDVB blend masks but v8i16/v16i16 aren't great either if PBLENDW fails) so I've limited this first patch to known non-zero cases if we can't easily use PBLENDW.
Differential Revision: https://reviews.llvm.org/D49562
llvm-svn: 338407
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp')
0 files changed, 0 insertions, 0 deletions
