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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-12-03 11:01:54 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-12-03 11:01:54 +0000
commitccc2a7c1a04a6ef8afa495bd64d72f766e62f24b (patch)
treeb7662de8858fde0f68f02535c9f7b0008c98e539 /llvm/lib/CodeGen/AsmPrinter/DIE.cpp
parenta48a12cf81cb0804506ddeb4994f17008cf097b3 (diff)
downloadbcm5719-llvm-ccc2a7c1a04a6ef8afa495bd64d72f766e62f24b.tar.gz
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[SystemZ] Fix choice of known-zero mask in insertion optimization
The backend converts 64-bit ORs into subreg moves if the upper 32 bits of one operand and the low 32 bits of the other are known to be zero. It then tries to peel away redundant ANDs from the upper 32 bits. Since AND masks are canonicalized to exclude known-zero bits, the test ORs the mask and the known-zero bits together before checking for redundancy. The problem was that it was using the wrong node when checking for known-zero bits, so could drop ANDs that were still needed. llvm-svn: 196267
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/DIE.cpp')
0 files changed, 0 insertions, 0 deletions
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