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| author | Craig Topper <craig.topper@intel.com> | 2019-07-01 19:01:37 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-07-01 19:01:37 +0000 |
| commit | 5e7815b695d4a21f021f23ed41750a44e9eb3849 (patch) | |
| tree | c51623980e785bd3c68f74b8a8bcfe87cf414486 /llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | |
| parent | b101c39f587731f0b36f264158e2ad8c7bbf5860 (diff) | |
| download | bcm5719-llvm-5e7815b695d4a21f021f23ed41750a44e9eb3849.tar.gz bcm5719-llvm-5e7815b695d4a21f021f23ed41750a44e9eb3849.zip | |
[X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
These instructions only read 64-bits of memory so we shouldn't
allow a full vector width load to be pattern matched in case it
is marked volatile.
Instead allow vzload or scalar_to_vector+load.
Also add a DAG combine to turn full vector loads into vzload when
used by one of these instructions if the load isn't volatile.
This fixes another case for PR42079
llvm-svn: 364838
Diffstat (limited to 'llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp')
0 files changed, 0 insertions, 0 deletions
