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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-24 14:05:39 +0000 | 
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-03-24 14:05:39 +0000 | 
| commit | a771fefb72a052b2f15b3ef65ffc7a0b1a9a525b (patch) | |
| tree | c8f5c944de9d437282f7a8ab610ee845129202ce /llvm/lib/CodeGen/Analysis.cpp | |
| parent | 227f5ed5473fcf076f664574ab69af9f07f9554b (diff) | |
| download | bcm5719-llvm-a771fefb72a052b2f15b3ef65ffc7a0b1a9a525b.tar.gz bcm5719-llvm-a771fefb72a052b2f15b3ef65ffc7a0b1a9a525b.zip | |
[mips] Implement shorthand add / sub forms for MIPS.
Summary:
- If only two registers are passed to a three-register operation, then the
  first argument is both source and destination register.
- If a non-register is passed as the last argument, generate the immediate
  version of the instruction.
Also mark DADD commutative and add scheduling information (to the generic
scheduler), and implement DSUB.
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL
CC: theraven
Differential Revision: http://llvm-reviews.chandlerc.com/D3148
llvm-svn: 204605
Diffstat (limited to 'llvm/lib/CodeGen/Analysis.cpp')
0 files changed, 0 insertions, 0 deletions

