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authorMatthias Braun <matze@braunis.de>2015-07-15 22:16:00 +0000
committerMatthias Braun <matze@braunis.de>2015-07-15 22:16:00 +0000
commit5d1f12d1f5e42cd538a245216529b7cae59d01a0 (patch)
tree93326a222da006a9568a8b97612451ab1c45ecca /llvm/lib/CodeGen/AllocationOrder.cpp
parent37643a04a499a61ad800bcb526fe36e74b0b3636 (diff)
downloadbcm5719-llvm-5d1f12d1f5e42cd538a245216529b7cae59d01a0.tar.gz
bcm5719-llvm-5d1f12d1f5e42cd538a245216529b7cae59d01a0.zip
TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints()
Pass a const reference to LiveRegMatrix to getRegAllocationHints() because some targets can prodive better hints if they can test whether a physreg has been used for register allocation yet. llvm-svn: 242340
Diffstat (limited to 'llvm/lib/CodeGen/AllocationOrder.cpp')
-rw-r--r--llvm/lib/CodeGen/AllocationOrder.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/AllocationOrder.cpp b/llvm/lib/CodeGen/AllocationOrder.cpp
index dc9bcff5612..40451c0d6c1 100644
--- a/llvm/lib/CodeGen/AllocationOrder.cpp
+++ b/llvm/lib/CodeGen/AllocationOrder.cpp
@@ -29,12 +29,13 @@ using namespace llvm;
// Compare VirtRegMap::getRegAllocPref().
AllocationOrder::AllocationOrder(unsigned VirtReg,
const VirtRegMap &VRM,
- const RegisterClassInfo &RegClassInfo)
+ const RegisterClassInfo &RegClassInfo,
+ const LiveRegMatrix *Matrix)
: Pos(0) {
const MachineFunction &MF = VRM.getMachineFunction();
const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
- TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
+ TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
rewind();
DEBUG({
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