diff options
author | Benjamin Kramer <benny.kra@googlemail.com> | 2015-07-18 20:05:10 +0000 |
---|---|---|
committer | Benjamin Kramer <benny.kra@googlemail.com> | 2015-07-18 20:05:10 +0000 |
commit | c9436ad6593a712f6544caf75fdd530cd06e58ac (patch) | |
tree | e91b11cd923b66e6ed5c10e5f1e15e3c344c5c95 /llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | |
parent | 3d49f6df9428ddcb8d07062a22a4a554e5f4abdc (diff) | |
download | bcm5719-llvm-c9436ad6593a712f6544caf75fdd530cd06e58ac.tar.gz bcm5719-llvm-c9436ad6593a712f6544caf75fdd530cd06e58ac.zip |
[AggressiveAntiDepBreaker] Use range loops for multimap access.
No functionality change intended.
llvm-svn: 242620
Diffstat (limited to 'llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp')
-rw-r--r-- | llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 31 |
1 files changed, 8 insertions, 23 deletions
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index 5fe4c4bcaec..fc5dcfae863 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -509,15 +509,8 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) { // Check all references that need rewriting for Reg. For each, use // the corresponding register class to narrow the set of registers // that are appropriate for renaming. - std::pair<std::multimap<unsigned, - AggressiveAntiDepState::RegisterReference>::iterator, - std::multimap<unsigned, - AggressiveAntiDepState::RegisterReference>::iterator> - Range = State->GetRegRefs().equal_range(Reg); - for (std::multimap<unsigned, - AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first, - QE = Range.second; Q != QE; ++Q) { - const TargetRegisterClass *RC = Q->second.RC; + for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) { + const TargetRegisterClass *RC = Q.second.RC; if (!RC) continue; BitVector RCBV = TRI->getAllocatableSet(MF, RC); @@ -685,9 +678,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also // defines 'NewReg' via an early-clobber operand. - auto Range = RegRefs.equal_range(Reg); - for (auto Q = Range.first, QE = Range.second; Q != QE; ++Q) { - auto UseMI = Q->second.Operand->getParent(); + for (const auto &Q : make_range(RegRefs.equal_range(Reg))) { + MachineInstr *UseMI = Q.second.Operand->getParent(); int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI); if (Idx == -1) continue; @@ -920,23 +912,16 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( // Update the references to the old register CurrReg to // refer to the new register NewReg. - std::pair<std::multimap<unsigned, - AggressiveAntiDepState::RegisterReference>::iterator, - std::multimap<unsigned, - AggressiveAntiDepState::RegisterReference>::iterator> - Range = RegRefs.equal_range(CurrReg); - for (std::multimap<unsigned, - AggressiveAntiDepState::RegisterReference>::iterator - Q = Range.first, QE = Range.second; Q != QE; ++Q) { - Q->second.Operand->setReg(NewReg); + for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) { + Q.second.Operand->setReg(NewReg); // If the SU for the instruction being updated has debug // information related to the anti-dependency register, make // sure to update that as well. - const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()]; + const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()]; if (!SU) continue; for (DbgValueVector::iterator DVI = DbgValues.begin(), DVE = DbgValues.end(); DVI != DVE; ++DVI) - if (DVI->second == Q->second.Operand->getParent()) + if (DVI->second == Q.second.Operand->getParent()) UpdateDbgValue(DVI->first, AntiDepReg, NewReg); } |