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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-01-09 17:31:07 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-01-09 17:31:07 +0000 |
| commit | 7d9bef8f5cf007af067d668fa1be86edf50e50c2 (patch) | |
| tree | 1d97f6f17b69a087cb2645b5bbe5318a5c358366 /llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | |
| parent | 4762c069dead49ba96c05da0b827f52fad117164 (diff) | |
| download | bcm5719-llvm-7d9bef8f5cf007af067d668fa1be86edf50e50c2.tar.gz bcm5719-llvm-7d9bef8f5cf007af067d668fa1be86edf50e50c2.zip | |
[CodeGen] Don't print "pred:" and "opt:" in -debug output
In -debug output we print "pred:" whenever a MachineOperand is a
predicate operand in the instruction descriptor, and "opt:" whenever a
MachineOperand is an optional def in the instruction descriptor.
Differential Revision: https://reviews.llvm.org/D41870
llvm-svn: 322096
Diffstat (limited to 'llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index ffcb9a09ad7..9ed7450d5cb 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -448,11 +448,11 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, // FIXME: The issue with predicated instruction is more complex. We are being // conservatively here because the kill markers cannot be trusted after // if-conversion: - // %r6 = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] + // %r6 = LDR %sp, %reg0, 92, 14, %reg0; mem:LD4[FixedStack14] // ... - // STR %r0, killed %r6, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395] - // %r6 = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12] - // STR %r0, killed %r6, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) + // STR %r0, killed %r6, %reg0, 0, 0, %cpsr; mem:ST4[%395] + // %r6 = LDR %sp, %reg0, 100, 0, %cpsr; mem:LD4[FixedStack12] + // STR %r0, killed %r6, %reg0, 0, 14, %reg0; mem:ST4[%396](align=8) // // The first R6 kill is not really a kill since it's killed by a predicated // instruction which may not be executed. The second R6 def may or may not |
