Enable first-class aggregates support.

Remove the GetResultInst instruction. It is still accepted in LLVM assembly
and bitcode, where it is now auto-upgraded to ExtractValueInst. Also, remove
support for return instructions with multiple values. These are auto-upgraded
to use InsertValueInst instructions.

The IRBuilder still accepts multiple-value returns, and auto-upgrades them
to InsertValueInst instructions.

llvm-svn: 53941

2 files changed, 27 insertions, 18 deletions

diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index 3e2af4f1725..f7796a6f9f4 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -1472,7 +1472,7 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
       Value *Op;
       getValueTypePair(Record, OpNum, NextValueNo, Op);
       unsigned Index = Record[1];
-      I = new GetResultInst(Op, Index);
+      I = ExtractValueInst::Create(Op, Index);
       break;
     }
     
@@ -1482,20 +1482,34 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
         if (Size == 0) {
           I = ReturnInst::Create();
           break;
-        } else {
-          unsigned OpNum = 0;
-          SmallVector<Value *,4> Vs;
-          do {
-            Value *Op = NULL;
-            if (getValueTypePair(Record, OpNum, NextValueNo, Op))
-              return Error("Invalid RET record");
-            Vs.push_back(Op);
-          } while(OpNum != Record.size());
-
-          // SmallVector Vs has at least one element.
-          I = ReturnInst::Create(&Vs[0], Vs.size());
+        }
+
+        unsigned OpNum = 0;
+        SmallVector<Value *,4> Vs;
+        do {
+          Value *Op = NULL;
+          if (getValueTypePair(Record, OpNum, NextValueNo, Op))
+            return Error("Invalid RET record");
+          Vs.push_back(Op);
+        } while(OpNum != Record.size());
+
+        const Type *ReturnType = F->getReturnType();
+        if (Vs.size() > 1 ||
+            (isa<StructType>(ReturnType) &&
+             (Vs.empty() || Vs[0]->getType() != ReturnType))) {
+          Value *RV = UndefValue::get(ReturnType);
+          for (unsigned i = 0, e = Vs.size(); i != e; ++i) {
+            I = InsertValueInst::Create(RV, Vs[i], i, "mrv");
+            CurBB->getInstList().push_back(I);
+            ValueList.AssignValue(I, NextValueNo++);
+            RV = I;
+          }
+          I = ReturnInst::Create(RV);
           break;
         }
+
+        I = ReturnInst::Create(Vs[0]);
+        break;
       }
     case bitc::FUNC_CODE_INST_BR: { // BR: [bb#, bb#, opval] or [bb#]
       if (Record.size() != 1 && Record.size() != 3)
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
index f4d73598b9f..2c585b13707 100644
--- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -768,11 +768,6 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
     Vals.push_back(VE.getValueID(I.getOperand(1)));
     Vals.push_back(cast<CmpInst>(I).getPredicate());
     break;
-  case Instruction::GetResult:
-    Code = bitc::FUNC_CODE_INST_GETRESULT;
-    PushValueAndType(I.getOperand(0), InstID, Vals, VE);
-    Vals.push_back(cast<GetResultInst>(I).getIndex());
-    break;
 
   case Instruction::Ret: 
     {