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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-09 18:43:29 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-09 18:43:29 +0000 |
| commit | 8bc05d7d603e3964c811fd65235f276858104fbb (patch) | |
| tree | e9118f3fdcc30762641f434771f9d6dac42d3cc4 /llvm/lib/Bitcode | |
| parent | d60ff75b562b56177dfe9337f123637bf904f884 (diff) | |
| download | bcm5719-llvm-8bc05d7d603e3964c811fd65235f276858104fbb.tar.gz bcm5719-llvm-8bc05d7d603e3964c811fd65235f276858104fbb.zip | |
AMDGPU: Make VReg_1 size be 1
This was getting chosen as the preferred 32-bit register class based
on how TableGen selects subregister classes.
llvm-svn: 371438
Diffstat (limited to 'llvm/lib/Bitcode')
0 files changed, 0 insertions, 0 deletions
