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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-03 23:32:29 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-03 23:32:29 +0000 |
| commit | 5b0922fe1f9dcecfc1f92bec21f1c8f3849daf31 (patch) | |
| tree | 4efcb11e276a69ade0afd31d75d2b0e124588cc1 /llvm/lib/Bitcode/Reader | |
| parent | 41ee3977c45a056011ffbdc2a7d31f59c18a7ae1 (diff) | |
| download | bcm5719-llvm-5b0922fe1f9dcecfc1f92bec21f1c8f3849daf31.tar.gz bcm5719-llvm-5b0922fe1f9dcecfc1f92bec21f1c8f3849daf31.zip | |
AMDGPU: Add pass to lower SGPR spills
This is split out from my patches to split register allocation into a
separate SGPR and VGPR phase, and has some parts that aren't yet used
(like maintaining LiveIntervals).
This simplifies making the frame pointer register callee saved. As it
is now, the code to determine callee saves needs to predict all the
possible SGPR spills and how many callee saved VGPRs are needed. By
handling this before PrologEpilogInserter, it's possible to just check
the spill objects that already exist.
Change-Id: I29e6df4034afcf949e06f8ef44206acb94696f04
llvm-svn: 365095
Diffstat (limited to 'llvm/lib/Bitcode/Reader')
0 files changed, 0 insertions, 0 deletions
