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| author | Geoff Berry <gberry@codeaurora.org> | 2018-01-24 18:09:53 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2018-01-24 18:09:53 +0000 |
| commit | c4796d474572a03c97d0ddac4584b65c3e0e267f (patch) | |
| tree | f23aaa1d3507a9beadc02a456199e02afa52811e /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 4afb64e4c601e89f0645deb86de3784f5ff2927b (diff) | |
| download | bcm5719-llvm-c4796d474572a03c97d0ddac4584b65c3e0e267f.tar.gz bcm5719-llvm-c4796d474572a03c97d0ddac4584b65c3e0e267f.zip | |
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
Summary:
Move reserveRegisterTuples into AMDGPURegisterInfo and use it in
R600RegisterInfo::getReservedRegs and
R600InstrInfo::reserveIndirectRegisters to ensure that all super
registers of reserved registers are also marked as reserved.
Before this change, under certain circumstances, the registers %t1_x and
%t1_xyzw would be marked as reserved, but %t1_xy and %t1_xyz would not
be, leading to the register allocator sometimes assigning a register to
%t1_xy, which is invalid since %t1_x is reserved.
Reviewers: arsenm, tstellar, MatzeB, qcolombet
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D42448
llvm-svn: 323356
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions
