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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 19:48:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 19:48:36 +0000 |
| commit | ad19b50c000762c2c7c50ad8f171cbc60ca060d0 (patch) | |
| tree | aa55770df48065f0e67e40db5f874f0ecfa377ed /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | e1b52f418033548601a7839cbbb8ceddc0751521 (diff) | |
| download | bcm5719-llvm-ad19b50c000762c2c7c50ad8f171cbc60ca060d0.tar.gz bcm5719-llvm-ad19b50c000762c2c7c50ad8f171cbc60ca060d0.zip | |
AMDGPU/GlobalISel: Don't constrain source register of VCC copies
This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.
This is necessary to successfully select branches with and and/or/xor
condition.
llvm-svn: 366120
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions
