Improvement to the previous fix: branch following a delay slot of

another delayed instr. would cause the later sanity-check (assertion)
in PhyRegAlloc.cpp to fail, even though there is really no error.

llvm-svn: 7848

1 files changed, 5 insertions, 3 deletions

diff --git a/llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp b/llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp
index 8cde6e1de7a..764ec36f37f 100644
--- a/llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp
+++ b/llvm/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp
@@ -290,9 +290,11 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
       for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
         assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
         MachineInstr* DelaySlotMI = *fwdMII;
-        set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
-        if (i+1 == DS)
-          set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
+        if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpCode())) {
+          set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
+          if (i+1 == DS)
+            set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
+        }
       }
     }