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| author | Craig Topper <craig.topper@intel.com> | 2019-02-28 07:21:26 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-02-28 07:21:26 +0000 |
| commit | 6ca7398a1e9481c950d60f2200b297fd9c2d67a7 (patch) | |
| tree | 8711e2d3ca544c123f317110ceb3554807fd47be /llvm/lib/Analysis/ValueTracking.cpp | |
| parent | e931931b34cebf132b601374399f021105434c32 (diff) | |
| download | bcm5719-llvm-6ca7398a1e9481c950d60f2200b297fd9c2d67a7.tar.gz bcm5719-llvm-6ca7398a1e9481c950d60f2200b297fd9c2d67a7.zip | |
[X86] Use PreprocessISelDAG to convert vector sra/srl/shl to the X86 specific variable shift ISD opcodes.
These allows use to use the same set of isel patterns for sra/srl/shl which are undefined for out of range shifts and intrinsic shifts which aren't undefined.
Doing this late allows DAG combine to have every opportunity to optimize the sra/srl/shl nodes.
This removes about 7000 bytes from the isel table and simplies the td files.
llvm-svn: 355071
Diffstat (limited to 'llvm/lib/Analysis/ValueTracking.cpp')
0 files changed, 0 insertions, 0 deletions
