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authorCraig Topper <craig.topper@intel.com>2019-09-05 18:15:07 +0000
committerCraig Topper <craig.topper@intel.com>2019-09-05 18:15:07 +0000
commitb8d6ba3ca203847be7cb3e4e2e352cf6c5502ca4 (patch)
treef1e31e2947b19ab9b1d8e588e594f42370b3e411 /llvm/lib/Analysis/SyntheticCountsUtils.cpp
parent00e04b0a6d51a415ea70133bbc2c6dad9cc72ecc (diff)
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[X86] Override BuildSDIVPow2 for X86.
As noted in PR43197, we can use test+add+cmov+sra to implement signed division by a power of 2. This is based off the similar version in AArch64, but I've adjusted it to use target independent nodes where AArch64 uses target specific CMP and CSEL nodes. I've also blocked INT_MIN as the transform isn't valid for that. I've limited this to i32 and i64 on 64-bit targets for now and only when CMOV is supported. i8 and i16 need further investigation to be sure they get promoted to i32 well. I adjusted a few tests to enable cmov to demonstrate the new codegen. I also changed twoaddr-coalesce-3.ll to 32-bit mode without cmov to avoid perturbing the scenario that is being set up there. Differential Revision: https://reviews.llvm.org/D67087 llvm-svn: 371104
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