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| author | Graham Sellers <graham.sellers@amd.com> | 2018-12-07 15:33:21 +0000 |
|---|---|---|
| committer | Graham Sellers <graham.sellers@amd.com> | 2018-12-07 15:33:21 +0000 |
| commit | b297379ef07829ac7f06c0e2058a889366c46a82 (patch) | |
| tree | f1f6b124bb90dfa8f870194377314a7ae57d0c40 /llvm/lib/Analysis/DemandedBits.cpp | |
| parent | 248ed074199e4aa65c706a11033de88da883856d (diff) | |
| download | bcm5719-llvm-b297379ef07829ac7f06c0e2058a889366c46a82.tar.gz bcm5719-llvm-b297379ef07829ac7f06c0e2058a889366c46a82.zip | |
[AMDGPU] Shrink scalar AND, OR, XOR instructions
This change attempts to shrink scalar AND, OR and XOR instructions which take an immediate that isn't inlineable.
It performs:
AND s0, s0, ~(1 << n) -> BITSET0 s0, n
OR s0, s0, (1 << n) -> BITSET1 s0, n
AND s0, s1, x -> ANDN2 s0, s1, ~x
OR s0, s1, x -> ORN2 s0, s1, ~x
XOR s0, s1, x -> XNOR s0, s1, ~x
In particular, this catches setting and clearing the sign bit for fabs (and x, 0x7ffffffff -> bitset0 x, 31 and or x, 0x80000000 -> bitset1 x, 31).
llvm-svn: 348601
Diffstat (limited to 'llvm/lib/Analysis/DemandedBits.cpp')
0 files changed, 0 insertions, 0 deletions
