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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-02-18 16:44:18 +0000 | 
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-02-18 16:44:18 +0000 | 
| commit | f2c64db55a851c41db9af373949b26d5a226973a (patch) | |
| tree | fd516c3c899015d1fcf582d3f369a04004b64f12 /llvm/include | |
| parent | 7a545536f56e0c7049c6f614b97e7573ceedf778 (diff) | |
| download | bcm5719-llvm-f2c64db55a851c41db9af373949b26d5a226973a.tar.gz bcm5719-llvm-f2c64db55a851c41db9af373949b26d5a226973a.zip  | |
AMDGPU/SI: add llvm.amdgcn.image.load/store[.mip] intrinsics
Summary:
These correspond to IMAGE_LOAD/STORE[_MIP] and are going to be used by Mesa
for the GL_ARB_shader_image_load_store extension.
IMAGE_LOAD is already matched by llvm.SI.image.load. That intrinsic has
a legacy name and pretends not to read memory.
Differential Revision: http://reviews.llvm.org/D17276
llvm-svn: 261224
Diffstat (limited to 'llvm/include')
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 29 | 
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index ef3c24080b8..54725c5b071 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -143,6 +143,35 @@ def int_amdgcn_cubetc : GCCBuiltin<"__builtin_amdgcn_cubetc">,      [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]  >; +class AMDGPUImageLoad : Intrinsic < +  [llvm_v4f32_ty],    // vdata(VGPR) +  [llvm_anyint_ty,    // vaddr(VGPR) +   llvm_v8i32_ty,     // rsrc(SGPR) +   llvm_i32_ty,       // dmask(imm) +   llvm_i1_ty,        // r128(imm) +   llvm_i1_ty,        // da(imm) +   llvm_i1_ty,        // glc(imm) +   llvm_i1_ty],       // slc(imm) +  [IntrReadMem]>; + +def int_amdgcn_image_load : AMDGPUImageLoad; +def int_amdgcn_image_load_mip : AMDGPUImageLoad; + +class AMDGPUImageStore : Intrinsic < +  [], +  [llvm_v4f32_ty,     // vdata(VGPR) +   llvm_anyint_ty,    // vaddr(VGPR) +   llvm_v8i32_ty,     // rsrc(SGPR) +   llvm_i32_ty,       // dmask(imm) +   llvm_i1_ty,        // r128(imm) +   llvm_i1_ty,        // da(imm) +   llvm_i1_ty,        // glc(imm) +   llvm_i1_ty],       // slc(imm) +  []>; + +def int_amdgcn_image_store : AMDGPUImageStore; +def int_amdgcn_image_store_mip : AMDGPUImageStore; +  def int_amdgcn_read_workdim : AMDGPUReadPreloadRegisterIntrinsic <    "__builtin_amdgcn_read_workdim">;  | 

