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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-01-22 03:32:36 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-01-22 03:32:36 +0000
commitbfdba5e4fc351d3de15d5536a1d4e04a16573ddf (patch)
tree0d1dff23cf739d81409b302850eea4d890fd16b9 /llvm/include
parent1eaa04d682d684f7e83c263aa40e78ae8faab378 (diff)
downloadbcm5719-llvm-bfdba5e4fc351d3de15d5536a1d4e04a16573ddf.tar.gz
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IR: Add fp operations to atomicrmw
Add just fadd/fsub for now. llvm-svn: 351778
Diffstat (limited to 'llvm/include')
-rw-r--r--llvm/include/llvm/Bitcode/LLVMBitCodes.h4
-rw-r--r--llvm/include/llvm/CodeGen/TargetLowering.h5
-rw-r--r--llvm/include/llvm/IR/Instructions.h22
3 files changed, 27 insertions, 4 deletions
diff --git a/llvm/include/llvm/Bitcode/LLVMBitCodes.h b/llvm/include/llvm/Bitcode/LLVMBitCodes.h
index e694331776c..ce853cd3998 100644
--- a/llvm/include/llvm/Bitcode/LLVMBitCodes.h
+++ b/llvm/include/llvm/Bitcode/LLVMBitCodes.h
@@ -406,7 +406,9 @@ enum RMWOperations {
RMW_MAX = 7,
RMW_MIN = 8,
RMW_UMAX = 9,
- RMW_UMIN = 10
+ RMW_UMIN = 10,
+ RMW_FADD = 11,
+ RMW_FSUB = 12
};
/// OverflowingBinaryOperatorOptionalFlags - Flags for serializing
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 3886ac54ed3..850b9e2d555 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1715,8 +1715,9 @@ public:
/// Returns how the IR-level AtomicExpand pass should expand the given
/// AtomicRMW, if at all. Default is to never expand.
- virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
- return AtomicExpansionKind::None;
+ virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
+ return RMW->isFloatingPointOperation() ?
+ AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
}
/// On some platforms, an AtomicRMW that never actually modifies the value
diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h
index c720dd8745e..beadf7313a2 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -724,8 +724,14 @@ public:
/// *p = old <unsigned v ? old : v
UMin,
+ /// *p = old + v
+ FAdd,
+
+ /// *p = old - v
+ FSub,
+
FIRST_BINOP = Xchg,
- LAST_BINOP = UMin,
+ LAST_BINOP = FSub,
BAD_BINOP
};
@@ -747,6 +753,16 @@ public:
static StringRef getOperationName(BinOp Op);
+ static bool isFPOperation(BinOp Op) {
+ switch (Op) {
+ case AtomicRMWInst::FAdd:
+ case AtomicRMWInst::FSub:
+ return true;
+ default:
+ return false;
+ }
+ }
+
void setOperation(BinOp Operation) {
unsigned short SubclassData = getSubclassDataFromInstruction();
setInstructionSubclassData((SubclassData & 31) |
@@ -804,6 +820,10 @@ public:
return getPointerOperand()->getType()->getPointerAddressSpace();
}
+ bool isFloatingPointOperation() const {
+ return isFPOperation(getOperation());
+ }
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::AtomicRMW;
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