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| author | Alex Bradbury <asb@lowrisc.org> | 2016-11-01 16:47:54 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2016-11-01 16:47:54 +0000 |
| commit | b6e784a240fa3f62874c457afa43be37278cfa2d (patch) | |
| tree | c531437838d70751037513e0734fbaef289438b4 /llvm/include | |
| parent | 586aeee3413efe710bb70df86e30119f28281e82 (diff) | |
| download | bcm5719-llvm-b6e784a240fa3f62874c457afa43be37278cfa2d.tar.gz bcm5719-llvm-b6e784a240fa3f62874c457afa43be37278cfa2d.zip | |
[RISCV] Recognise riscv32 and riscv64 in triple parsing code
This is the first in a series of 10 initial patches that incrementally add an
MC layer for RISC-V to LLVM. See
<http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html> for more
discussion.
Differential Revision: https://reviews.llvm.org/D23557
llvm-svn: 285707
Diffstat (limited to 'llvm/include')
| -rw-r--r-- | llvm/include/llvm/ADT/Triple.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h index 2255a7cbc5c..9d57cdcd83b 100644 --- a/llvm/include/llvm/ADT/Triple.h +++ b/llvm/include/llvm/ADT/Triple.h @@ -64,6 +64,8 @@ public: ppc64le, // PPC64LE: powerpc64le r600, // R600: AMD GPUs HD2XXX - HD6XXX amdgcn, // AMDGCN: AMD GCN GPUs + riscv32, // RISC-V (32-bit): riscv32 + riscv64, // RISC-V (64-bit): riscv64 sparc, // Sparc: sparc sparcv9, // Sparcv9: Sparcv9 sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant |
