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author | Dan Gohman <gohman@apple.com> | 2008-11-20 01:26:25 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2008-11-20 01:26:25 +0000 |
commit | 4ce15e12b9a5c3d8ca43334fef159dfb98a0c94e (patch) | |
tree | d0ef994eec6801c00901b4231d3146e3924d3b3f /llvm/include | |
parent | c8b2fe1eeda436a9a855ac9ffc34a3ec9f5b1ac8 (diff) | |
download | bcm5719-llvm-4ce15e12b9a5c3d8ca43334fef159dfb98a0c94e.tar.gz bcm5719-llvm-4ce15e12b9a5c3d8ca43334fef159dfb98a0c94e.zip |
Factor out the code for verifying the work of the scheduler,
extend it a bit, and make use of it in all schedulers, to
ensure consistent checking.
llvm-svn: 59689
Diffstat (limited to 'llvm/include')
-rw-r--r-- | llvm/include/llvm/CodeGen/ScheduleDAG.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h index ee252033ada..e225953a29d 100644 --- a/llvm/include/llvm/CodeGen/ScheduleDAG.h +++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h @@ -96,7 +96,7 @@ namespace llvm { Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), isPending(false), isAvailable(false), isScheduled(false), - CycleBound(0), Cycle(0), Depth(0), Height(0), + CycleBound(0), Cycle(~0u), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} /// SUnit - Construct an SUnit for post-regalloc scheduling to represent @@ -106,7 +106,7 @@ namespace llvm { Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), isPending(false), isAvailable(false), isScheduled(false), - CycleBound(0), Cycle(0), Depth(0), Height(0), + CycleBound(0), Cycle(~0u), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} /// setNode - Assign the representative SDNode for this SUnit. @@ -308,6 +308,12 @@ namespace llvm { /// the ScheduleDAG. virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const {} +#ifndef NDEBUG + /// VerifySchedule - Verify that all SUnits were scheduled and that + /// their state is consistent. + void VerifySchedule(bool isBottomUp); +#endif + protected: void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO); |