[RegBankSelect] Initial implementation for non-optimized output.

The pass walk through the machine function and assign the register banks
using the default mapping. In other words, there is no attempt to reduce
cross register copies.

llvm-svn: 265707

1 files changed, 49 insertions, 16 deletions

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
index 9634f0a610e..57137ec5fb8 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
@@ -64,11 +64,13 @@
 #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H
 #define LLVM_CODEGEN_GLOBALISEL_REGBANKSELECT_H
 
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 
 namespace llvm {
 // Forward declarations.
-class RegisterBankInfo;
+class MachineRegisterInfo;
 
 /// This pass implements the reg bank selector pass used in the GlobalISel
 /// pipeline. At the end of this pass, all register operands have been assigned
@@ -81,6 +83,29 @@ private:
   /// to register banks.
   const RegisterBankInfo *RBI;
 
+  /// MRI contains all the register class/bank information that this
+  /// pass uses and updates.
+  MachineRegisterInfo *MRI;
+
+  /// Helper class used for every code morphing.
+  MachineIRBuilder MIRBuilder;
+
+  /// Assign the register bank of each operand of \p MI.
+  void assignInstr(MachineInstr &MI);
+
+  /// Initialize the field members using \p MF.
+  void init(MachineFunction &MF);
+
+  /// Check if \p Reg is already assigned what is described by \p ValMapping.
+  bool assignmentMatch(unsigned Reg,
+                       const RegisterBankInfo::ValueMapping &ValMapping) const;
+
+  /// Insert repairing code to map \p Reg as specified by \p ValMapping.
+  /// The repairing code is inserted where the MIRBuilder points.
+  /// \return The register of the properly mapped value.
+  unsigned repairReg(unsigned Reg,
+                     const RegisterBankInfo::ValueMapping &ValMapping);
+
 public:
   // Ctor, nothing fancy.
   RegBankSelect();
@@ -89,21 +114,29 @@ public:
     return "RegBankSelect";
   }
 
-  // Simplified algo:
-  //   RBI = MF.subtarget.getRegBankInfo()
-  //   MIRBuilder.reset(MF)
-  //   for each bb in MF
-  //     for each inst in bb
-  //       MappingCosts = RBI.getMapping(inst);
-  //       Idx = findIdxOfMinCost(MappingCosts)
-  //       CurRegBank = MappingCosts[Idx].RegBank
-  //       MRI.setRegBank(inst.getOperand(0).getReg(), CurRegBank)
-  //       for each argument in inst
-  //         if (CurRegBank != argument.RegBank)
-  //           ArgReg = argument.getReg()
-  //           Tmp = MRI.createNewVirtual(MRI.getSize(ArgReg), CurRegBank)
-  //           MIRBuilder.buildInstr(COPY, Tmp, ArgReg)
-  //           inst.getOperand(argument.getOperandNo()).setReg(Tmp)
+  /// Walk through \p MF and assign a register bank to every virtual register
+  /// that are still mapped to nothing.
+  /// The target needs to provide a RegisterBankInfo and in particular
+  /// override RegisterBankInfo::getInstrMapping.
+  ///
+  /// Simplified algo:
+  /// \code
+  ///   RBI = MF.subtarget.getRegBankInfo()
+  ///   MIRBuilder.setMF(MF)
+  ///   for each bb in MF
+  ///     for each inst in bb
+  ///       MIRBuilder.setInstr(inst)
+  ///       MappingCosts = RBI.getMapping(inst);
+  ///       Idx = findIdxOfMinCost(MappingCosts)
+  ///       CurRegBank = MappingCosts[Idx].RegBank
+  ///       MRI.setRegBank(inst.getOperand(0).getReg(), CurRegBank)
+  ///       for each argument in inst
+  ///         if (CurRegBank != argument.RegBank)
+  ///           ArgReg = argument.getReg()
+  ///           Tmp = MRI.createNewVirtual(MRI.getSize(ArgReg), CurRegBank)
+  ///           MIRBuilder.buildInstr(COPY, Tmp, ArgReg)
+  ///           inst.getOperand(argument.getOperandNo()).setReg(Tmp)
+  /// \endcode
   bool runOnMachineFunction(MachineFunction &MF) override;
 };
 } // End namespace llvm.