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authorDiana Picus <diana.picus@linaro.org>2017-07-05 11:32:12 +0000
committerDiana Picus <diana.picus@linaro.org>2017-07-05 11:32:12 +0000
commit3e40b46bf0a31d5cddf0187de96b4d40c0cc2c2f (patch)
treec30e100bf415a67802463ed37b0d99bbd44e93c4 /llvm/include
parent55e2f5963aa146c8726650d33df0de072a2eba4c (diff)
downloadbcm5719-llvm-3e40b46bf0a31d5cddf0187de96b4d40c0cc2c2f.tar.gz
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[MachineIRBuilder] Add buildOr helper. NFC.
This isn't used anywhere yet, but I need it for a future commit. llvm-svn: 307141
Diffstat (limited to 'llvm/include')
-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 72a21bf9fbd..46ef0af303d 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -296,6 +296,19 @@ public:
MachineInstrBuilder buildAnd(unsigned Res, unsigned Op0,
unsigned Op1);
+ /// Build and insert \p Res<def> = G_OR \p Op0, \p Op1
+ ///
+ /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
+ /// Op1.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
+ /// with the same (scalar or vector) type).
+ ///
+ /// \return a MachineInstrBuilder for the newly created instruction.
+ MachineInstrBuilder buildOr(unsigned Res, unsigned Op0,
+ unsigned Op1);
+
/// Build and insert \p Res<def> = G_ANYEXT \p Op0
///
/// G_ANYEXT produces a register of the specified width, with bits 0 to
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