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| author | Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> | 2016-10-14 04:03:49 +0000 |
|---|---|---|
| committer | Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> | 2016-10-14 04:03:49 +0000 |
| commit | ee68fdadfe9665fafdc6d60e535879e2d1464f93 (patch) | |
| tree | 70974d56d9e21982419d875fbacac15ab0465566 /llvm/docs | |
| parent | e1f094546d40c9f563b5a0140ac3c3077a669be9 (diff) | |
| download | bcm5719-llvm-ee68fdadfe9665fafdc6d60e535879e2d1464f93.tar.gz bcm5719-llvm-ee68fdadfe9665fafdc6d60e535879e2d1464f93.zip | |
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations
Added relocation names:
- R_AMDGPU_GOTPCREL32_LO
- R_AMDGPU_GOTPCREL32_HI
- R_AMDGPU_REL32_LO
- R_AMDGPU_REL32_HI
AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above.
Differential Revision: https://reviews.llvm.org/D25546
llvm-svn: 284191
Diffstat (limited to 'llvm/docs')
| -rw-r--r-- | llvm/docs/CodeGenerator.rst | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/llvm/docs/CodeGenerator.rst b/llvm/docs/CodeGenerator.rst index 9fccaa07156..6e5a54a592c 100644 --- a/llvm/docs/CodeGenerator.rst +++ b/llvm/docs/CodeGenerator.rst @@ -2682,15 +2682,19 @@ Following notations are used for specifying relocation calculations: AMDGPU Backend generates *Elf64_Rela* relocation records with the following supported relocation types: - ===================== ===== ========== ==================== - Relocation type Value Field Calculation - ===================== ===== ========== ==================== - ``R_AMDGPU_NONE`` 0 ``none`` ``none`` - ``R_AMDGPU_ABS32_LO`` 1 ``word32`` (S + A) & 0xFFFFFFFF - ``R_AMDGPU_ABS32_HI`` 2 ``word32`` (S + A) >> 32 - ``R_AMDGPU_ABS64`` 3 ``word64`` S + A - ``R_AMDGPU_REL32`` 4 ``word32`` S + A - P - ``R_AMDGPU_REL64`` 5 ``word64`` S + A - P - ``R_AMDGPU_ABS32`` 6 ``word32`` S + A - ``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P - ===================== ===== ========== ==================== + ========================== ===== ========== ============================== + Relocation type Value Field Calculation + ========================== ===== ========== ============================== + ``R_AMDGPU_NONE`` 0 ``none`` ``none`` + ``R_AMDGPU_ABS32_LO`` 1 ``word32`` (S + A) & 0xFFFFFFFF + ``R_AMDGPU_ABS32_HI`` 2 ``word32`` (S + A) >> 32 + ``R_AMDGPU_ABS64`` 3 ``word64`` S + A + ``R_AMDGPU_REL32`` 4 ``word32`` S + A - P + ``R_AMDGPU_REL64`` 5 ``word64`` S + A - P + ``R_AMDGPU_ABS32`` 6 ``word32`` S + A + ``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P + ``R_AMDGPU_GOTPCREL32_LO`` 8 ``word32`` (G + GOT + A - P) & 0xFFFFFFFF + ``R_AMDGPU_GOTPCREL32_HI`` 9 ``word32`` (G + GOT + A - P) >> 32 + ``R_AMDGPU_REL32_LO`` 10 ``word32`` (S + A - P) & 0xFFFFFFFF + ``R_AMDGPU_REL32_HI`` 11 ``word32`` (S + A - P) >> 32 + ========================== ===== ========== ============================== |
